1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a stack-layer-structured semiconductor memory device using variable resistors.
2. Description of the Related Art
Electrically erasable programmable nonvolatile memories include a flash memory as well known in the art, which comprises a memory cell array of NAND-connected or NOR-connected memory cells having a floating gate structure. A ferroelectric memory is also known as a nonvolatile fast random access memory.
On the other hand, technologies of patterning memory cells much finer include a resistance variable memory, which uses a variable resistor in a memory cell as proposed. Known examples of the variable resistor include a phase change memory element that varies the resistance in accordance with the variation in crystal/amorphous states of a chalcogenide compound; an MRAM element that uses a variation in resistance due to the tunnel magneto-resistance effect; a polymer ferroelectric RAM (PFRAM) memory element including resistors formed of a conductive polymer; and a ReRAM element that causes a variation in resistance on electrical pulse application (Patent Document 1: JP 2006-344349A, paragraph 0021).
The resistance variable memory may configure a memory cell with a serial circuit of a Schottky diode and a resistance variable element in place of the transistor. Accordingly, it can be stacked easier and three-dimensionally structured to achieve much higher integration advantageously (Patent Document 2: JP 2005-522045A).
A semiconductor memory device having a stack-layered structure comprises memory layers, which differ in thermal history resulted from the process of stacking layers. Namely, the lower the memory layer, the more it is susceptible to heat. As a result, the oxidation degrees of the metal oxide vary among the memory layers and cause differences in write characteristic among the memory cells.